author = "Sutter, Gustavo"

Encontrado 12 documentos, página mostrada 1 de 2

Aportes a la reducción de consumo en FPGAs

Author(s): Sutter, Gustavo D.
Description: Tesis doctoral inédita leída en la Universidad Autónoma de Madrid. Escuela Politécnica Superior, Departamento de Ingeniería Informática. Fecha de lectura: 15-04-2005
Language(s): Español

Low-power FSMs in FPGA: Encoding alternatives

Description: The final publication is available at Springer via http://dx.doi.org/10.1007/3-540-45716-X_36 , Proceedings of 12th International Workshop, PATMOS 2002 Seville, Spain, September 11–13, 2002 , In this paper, the problem of state encoding of FPGA-based synchronous finite state machines (FSMs) for low-power ...
Language(s): Inglés

FSM decomposition for low power in FPGA

Description: The final publication is available at Springer via http://dx.doi.org/10.1007/3-540-46117-5_37 , Proceedings of 12th International Conference, FPL 2002 Montpellier, France, September 2–4, 2002 , In this paper, the realization of low power finite state machines (FSMs) on FPGAs using decomposition techniques...
Language(s): Inglés

High resolution pulse width modulators in FPGA

Description: Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lis...
Language(s): Inglés

Implementación de Circuitos Self-Timed de 2 y 4 Fases en FPGAs

Description: Versión electrónica de la ponencia presentada en Jornadas de Computación Reconfigurable y Aplicaciones, celebrado en Madrid en 2003 , Aunque los dispositivos programables tipo FPGAs están diseñados para la implementación eficiente de circuitos síncronos, en la actualidad constituyen la única opción dis...
Language(s): Español

A tool for activity estimation in FPGAs

Description: The final publication is available at Springer via http://dx.doi.org/10.1007/3-540-46117-5_36 , In this paper, an activity estimation tool for FPGA-based combinational circuits is presented. The current version is able to estimate average activity for individual nodes. The tool is statistical-based, al...
Language(s): Inglés

High-speed FPGA 10's complement adders-subtractors

Description: This paper first presents a study on the classical BCD adders from which a carry-chain type adder is redesigned to fit within the Xilinx FPGA's platforms. Some new concepts are presented to compute the P and G functions for carry-chain optimization purposes. Several alternative designs are presented...
Language(s): Inglés

Accurate and affordable packet-train testing systems for multi-gigabit-per-second networks

Description: Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lis...
Language(s): Inglés

Encontrado 12 documentos, página mostrada 1 de 2

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